The present invention relates to SRAM cells generally and, more particularly, to a non-volatile SRAM cell that can be manufactured using a conventional floating-gate (e.g., EPROM, EEPROM or flash) or floating charge storage layer (e.g., SONOS or MNOS) technology. The present non-volatile SRAM cell may also function as a combination ROM-RAM cell (e.g., where the cell provides a ROM function on power-up and a RAM function under normal operating conditions).
One example of a conventional non-volatile SRAM cell can be found in U.S. Pat. No. 5,488,579, which is hereby incorporated by reference in its entirety. The cell of the 579 patent includes a three transistor non-volatile stack (i.e., with source-drain terminals in series), but does not shunt the SRAM pass transistor. The pass transistors also receive a second positive supply voltage, Vdd2, that differs from a conventional first positive supply voltage (e.g., Vcc or Vdd1). The stack is made up of PMOS transistors, with a PMOS SONOS device occupying the middle position.
The 579 patent has one or more of the following disadvantages: (i) a two-cycle cell that requires CLEAR and STORE non-volatile operations on power-fail in the worst case scenario, (ii) the cell is less suitable for combination ROM/SRAM due to potential finite disturb problems, and/or (iii) the cell has little margin for error (e.g., one must take significant care on RECALL to weaken the volatile latch for correct transfer of non-volatile data).
The present invention concerns a non-volatile SRAM cell, comprising (i) a nonvolatile memory element; (ii) a volatile memory element coupled to the nonvolatile memory element; and (iii) a gate circuit coupled to the nonvolatile memory element, wherein the gate circuit is configured to transfer data to and from a first input/output line into the volatile memory element.
Another aspect of the present invention concerns a method for recalling data previously stored in a volatile memory, comprising the sequential steps of: (a) storing the data in a non-volatile memory element coupled to the volatile memory upon a power fail event; (b) applying power to a device containing both the non-volatile memory element and the volatile memory; and (c) recalling said data from said non-volatile memory element into said volatile memory. In one embodiment of this aspect, the method recalling step comprises the steps of: (c-1) writing a predetermined digital logic value into the volatile memory, and (c-2) reading the non-volatile memory element.
The objects, features and advantages of the present invention include a non-volatile static memory cell that comprises a conventional SPAM cell and control circuitry, with (i) only one or two additional non-volatile transistors, (ii) only two extra control lines and a controlled power/voltage supply, and/or (iii) non-volatile memory elements that do not interfere with normal SRAM operation.